Memory address remapping

[Steve]

Hi all,

I am having some difficulty understanding how memory remapping is
carried out in the ARM926 core. I understand that upon boot, the CPU
reads data from Flash, or some non-volatile memory, that has been
mapped to address 0, and that after initialisation, it is generally the
case that the CPU remaps the memory regions so that the address 0 is
mapped to volatile memory, such as SRAM, so that the interrupt vectors
can be modified during execution.

The problem I am having is understanding the means with which this is
achieved. I have heard the term MMU and MPU banded about as the
solution to this problem but I'm wary about going down this avenue
because at the moment I'm really trying to minimise the complexity of
the software. Also, in the book I'm working from, ARM System
Developer's Guide (Blue book), the chapter on Firmware preceeds that on
the MMU and MPU, and it appears that the source code from it, which
does some mapping, does not refer to any of these blocks. Could someone
give me some pointers on how this is done?

Thanks,

Stephen Henry

[Will]

Post by Steve
Hi all,
I am having some difficulty understanding how memory
remapping is carried out in the ARM926 core. I understand
that upon boot, the CPU reads data from Flash, or some
non-volatile memory, that has been mapped to address 0, and
that after initialisation, it is generally the case that
the CPU remaps the memory regions so that the address 0 is
mapped to volatile memory, such as SRAM, so that the
interrupt vectors can be modified during execution.

The ARM boots from 0x0, so during boot this address must
contain code, i.e. be non-volatile. If you hard code your
instruction vectors then everyone is happy, except flash is
usually slower than RAM.
If you want fast ram at zero then some remapping has to
happen, this is usually done one of three ways:

1: Using an MMU you can map virtual memory to physical memory
in any number of diffrent ways, in block sizes down to 1k
2: Using a core with TCM, the TCm may be switched on at zero,
hiding the memory that was otherwise at zero.
3: In simple designs you may have a line which causes memory
at another address to be alaised at zero, when you are booting
you branch to the code at the high address and switch off the
alias.

Post by Steve
I have heard the term MMU and MPU
banded about as the solution to this problem

MPU's do not allow remapping of memory

Post by Steve
but I'm wary
about going down this avenue because at the moment I'm
really trying to minimise the complexity of the software.

you are stuck with the way that the chip manufactur has
decided to allow you to work. For simple systems you can get
away with running the code from ROM, and this will work on
almost any chip, if you don't want to do this then you will
have to work with the mechanism you have available.


HTH
Will

[Joseph]

Post by Will
1: Using an MMU you can map virtual memory to physical memory
in any number of diffrent ways, in block sizes down to 1k
2: Using a core with TCM, the TCm may be switched on at zero,
hiding the memory that was otherwise at zero.
3: In simple designs you may have a line which causes memory
at another address to be alaised at zero, when you are booting
you branch to the code at the high address and switch off the
alias.

Thanks Will for the answer.

A little bit more information to add:
Regarding item 3, if you look at figure 1.5 (page 14) of the
ARM System Developer's Guide, it have a brief descriptions there.

This is commonly used for ARM7 and ARM9 SoC. The switching is
controlled by a peripheral register (typically called REMAP).
This remapping is done at the physical address level (not on
logical address as see by CPU core), and usually be carried out
by boot loader before starting your embedded OS, so your OS and
applications only need to know about the memory map after the
remap change.

The remap control signal controls the AHB decoder in the
AMBA bus system, so that the HSEL generation behave differently
when the remap is switched. You can find more information on this
topic in "AHB Example AMBA System"
http://www.arm.com/pdfs/DDI0170A.zip
Section 4.3.2 and section 5.2

regards,
Joseph

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[Steve]

Thanks,

I understand what's happening now,

Stephen