LDR r0,=0xFFFFFFFF what does the "="mean?

[khoa nguyen]

I found this line of code LDR r0,=0xFFFFFFFF in one of the testbenches
at the site: www.foo.be/docs-free/nnARM/Testbench/Testbench.html

I've checked on the ARM ISA Quick Guide, but could not decipher what
the "=" in the instruction is for.

Also I am trying to acquire some test benches for a final year
project. Im trying to implement the ARM ISA on an fpga, and thought
that if any of you have some test benches or small applications lying
around then could you direct me to them.

thanks.

[Kevin Bracey]

Post by khoa nguyen
I found this line of code LDR r0,=0xFFFFFFFF in one of the testbenches
at the site: www.foo.be/docs-free/nnARM/Testbench/Testbench.html
I've checked on the ARM ISA Quick Guide, but could not decipher what
the "=" in the instruction is for.

It's a pseudo-instruction to the assembler. You can't load an arbitrary
32-bit constant directly (because each instruction is only 32 bits in size).
Instead you have to either assemble difficult constants in multiple
instructions or load them from a literal pool.

The LDR Rd,=xxxxx construct tells the assembler to generate either a MOV
Rd,#xxxxx or MVN Rd,#:NOT:xxxxx instruction, if possible, else to generate a
PC-relative LDR from a literal pool. The literal pool will be automatically
inserted at the end of your area, or can be dumped out with the LTORG
directive.

In this case, the assembler will generate MVN r0, #0.

[khoa nguyen]

Post by Kevin Bracey

Post by khoa nguyen
I found this line of code LDR r0,=0xFFFFFFFF in one of the testbenches
at the site: www.foo.be/docs-free/nnARM/Testbench/Testbench.html
I've checked on the ARM ISA Quick Guide, but could not decipher what
the "=" in the instruction is for.

It's a pseudo-instruction to the assembler. You can't load an arbitrary
32-bit constant directly (because each instruction is only 32 bits in size).
Instead you have to either assemble difficult constants in multiple
instructions or load them from a literal pool.
The LDR Rd,=xxxxx construct tells the assembler to generate either a MOV
Rd,#xxxxx or MVN Rd,#:NOT:xxxxx instruction, if possible, else to generate a
PC-relative LDR from a literal pool. The literal pool will be automatically
inserted at the end of your area, or can be dumped out with the LTORG
directive.
In this case, the assembler will generate MVN r0, #0.

Thank you Kevin for your clarification. Could you direct me to where
you obtained the above information. I thought that it would be useful
should I have more trouble.

thanks again,
khoa.

[Ahmed S. Badran]

Check the ADS Assembler Guide, section 4.9 ARM pseudo-instructions.

Regards,
Ahmed

Post by khoa nguyen

Post by Kevin Bracey

Post by khoa nguyen
I found this line of code LDR r0,=0xFFFFFFFF in one of the testbenches
at the site: www.foo.be/docs-free/nnARM/Testbench/Testbench.html
I've checked on the ARM ISA Quick Guide, but could not decipher what
the "=" in the instruction is for.

It's a pseudo-instruction to the assembler. You can't load an arbitrary
32-bit constant directly (because each instruction is only 32 bits in size).
Instead you have to either assemble difficult constants in multiple
instructions or load them from a literal pool.
The LDR Rd,=xxxxx construct tells the assembler to generate either a MOV
Rd,#xxxxx or MVN Rd,#:NOT:xxxxx instruction, if possible, else to generate a
PC-relative LDR from a literal pool. The literal pool will be automatically
inserted at the end of your area, or can be dumped out with the LTORG
directive.
In this case, the assembler will generate MVN r0, #0.

Thank you Kevin for your clarification. Could you direct me to where
you obtained the above information. I thought that it would be useful
should I have more trouble.
thanks again,
khoa.